1. Fields of the Invention
The present invention relates to a fixed-outline floorplanning approach for mixed-size modules, especially by means of evenly distributing circuit modules over a chip outline in the global distribution stage based on different requirements, such as wire-length, thermal, routability, performance and so on, and removing the overlap between circuit modules in a legalization stage without violating relative positions of the modules determined in the global distribution results and the fixed-outline constraint, so as to save the wire-length of the chip, enhance the chip performance and shorten the time of IC design flow.
2. Descriptions of Related Art
Floorplanning, which determines the shapes and locations of modules in a chip, is an important step in VLSI design, and chip performance is deeply affected by the results. In order to reduce design complexity, hierarchical designs are widely applied approaches on SoCs, which makes floorplanning more important than ever. Since a good floorplanning usually leads to a better distribution of module locations, total routing length can be reduced, which not only enhances the chip performance, but also significantly shorten the time to market for ICs design.
The properties of analog and digital modules are different. Since a digital module is usually made by automatic distributed winding tools, it is called a soft module, in which the aspect ratio of the shape of the module is able to be changed on the premise of area unchanged. However, a hard module generally refers to a custom design module such as an analog circuit module. Because it is manually drafted by engineers, its aspect ratio cannot be changed. Currently, engineers still have to complete floorplanning semi-manually by use of a prevailing tool SoC Encounter in the industry, which is greatly relied on layout designers' experiences and wisdom. In other words, full automation in this regard is not available.
In previous researches, most of them apply the simulated annealing algorithm to handle floorplanning. Because the simulated annealing algorithm is non-deterministic, it not only takes longer execution time, but also obtains different results in each time.
Recently, Yan and Chu proposed a floorplanning approach (DeFer: Deferred decision making enable fixed-outline floor-planner, In Proc. DAC, pp. 161-166, in 2008), which first build a generalized slicing tree by applying hMetis to partition circuit modules, and then merges curves of nodes in the tree to build a floorplan. Although DeFer is efficient and effective, it has two major disadvantages as follows: (1) it can obtain good result while only wire-length is considered. That is, DeFer is hard to be extended to consider other factors such as thermal and routability, which are important issues in modern designs. (2) It uses a random process in its method which leads to different results each time it is executed.
In order to solve above problems, to optimize several objectives including smaller chip area and shorter routing wire-length under the fixed-outline constraint, and to get the stable results in quick running time, there is room for improvement and a need to provide a novel method.